1. Field of the Invention
The present invention relates to a floating point execution unit having a canceling prediction circuit and a prediction error detection circuit for judging the necessary of the shifting for the compensation of one bit error, and more particularly, the invention relates to a method to perform the arithmetic operation at high speed.
2. Description of the Related Art
In order to true up or justify leftward the most significant bit of a mantissa part onto a particular position or digit, a normalization process is needed in a floating point execution unit after the calculation operation of addition and subtraction has been completed. This normalization process is such a process that the number of xe2x80x9c0""sxe2x80x9d or xe2x80x9c1""sxe2x80x9d which are aligned continuously from the most significant digits of the arithmetic result are counted and then the arithmetic result is shifted leftward by digits corresponding to the counted number of leading xe2x80x9c0""sxe2x80x9d or xe2x80x9c1""sxe2x80x9d.
With the progress of the processor speed, such a method has been proposed that enables to predict the number of xe2x80x9c0""sxe2x80x9d or xe2x80x9c1""sxe2x80x9d which are aligned continuously from the most significant digits of the arithmetic result in parallel with the calculation process (LZA: Leading Zero Anticipation method, a canceling prediction method or a canceling prediction circuit). This canceling prediction method has been set forth in papers published by E. HOKENEK (IBM, J. RES. DEVELP. VOL.34, 1990, pp.71-77), H. SUZUKI et al.(CICC Cproc., 1995, pp.27.5.1-27.5.4), etc.
The basic conception of the canceling prediction method of E. HOKENEK briefly will be explained below.
First, corresponding bits in mantissa parts of two operands are compared. Second, three inputs G, Z, and P are defined based on the comparison result of each comparison operation. The G-inputs indicates that corresponding bits are both xe2x80x9c1xe2x80x9d. The Z-inputs indicates that corresponding bits are both xe2x80x9c0xe2x80x9d. The P-inputs indicates that corresponding bits are xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. Because each comparison result has one of the G-inputs, Z-inputs, and P-inputs, the canceling bit at which canceling occurs can be specified when the comparison results of the corresponding bits of the mantissa parts are detected from the most significant bit to the least significant bit according to the state transition diagram shown in FIG. 1.
For example, the following subtraction will be considered:
1.00010000000000010000000=Fa less than 23:0 greater than xe2x88x92) 1.00001111000000000000000=Fb less than 23:0 greater than 
0.00000001000000010000000
An actual operation for the above subtraction performs an addition between Fa less than 23:0 greater than  and a complement on Fb less than 23:0 greater than  are added. The complement on Fb less than 23:0 greater than  is obtained by adding the least significant bit A1xe2x80x3 to Fbx less than 23:0 greater than  obtained by inverting Fb less than 23:0 greater than .
That is to say,
1.00010000000000010000000=Fa less than 23:0 greater than +) 0.11110000111111111111111=Fbx less than 23:0 greater than 
0.00000001000000001111111
In addition,
0.00000001000000001111111+) 1
0.00000001000000010000000
The result of this arithmetic operation has the canceling of 8 bits. In general, the canceling prediction in order to predict the canceling is performed with subtraction operation in parallel.
Firstly, when each bit in the result of the arithmetic operation described above is defined with the three inputs, G (both xe2x80x9c1xe2x80x9d), Z (both xe2x80x9c0xe2x80x9d), and P (xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d), the following result is obtained.
xe2x80x831.00010000000000010000000=Fa less than 23:0 greater than +) 0.1111000011111111111111=Fbx less than 23:0 greater than 
P.PPPGZZZZPPPPPPPGPPPPPPP
0.00000001000000010000000=EE less than 23:0 greater than 
When the above result (P.PPPGZZZZPPPPPPPGPPPPPPP) is checked from the most significant bit to the least significant bit based on the state transition diagram shown in FIG. 1, the P state is repeated in the pattern xe2x80x9cP.PPPxe2x80x9d,the following inputs pattern xe2x80x9cGxe2x80x9d transits from the P state to the G state. Then, the Z state is repeated in the pattern xe2x80x9cZZZZxe2x80x9d. The canceling is detected at the following P state.
In the paper of H. SUZUKI, only signals (canceling prediction bit signals) are extracted. These signals are so predicted that the: canceling from the Z state shown in FIG. 1 occurs. Then, a priority encoder detects the most significant bit in these signals.
This operation realizes the logic to generate the canceling prediction bit signal based on that the difference of mantissa parts in two operands have already been known. Because the two operands are switched in order to obtain the positive result of, subtraction when subtraction is performed, there is no transition to the G state.
That is, canceling occurs only when the symbol pattern in the alignment of the result changes from the Z-inputs to the P-inputs (Zxe2x86x92P) or the G-inputs (Zxe2x86x92G). This meaning is defined by using the following logic:
EE less than i greater than =(Z less than i greater than  and G less than ixe2x88x921 greater than ) or (Z less than i greater than  and P less than ixe2x88x921 greater than ).
Thus, the canceling bit prediction signal EE less than i greater than  can be generated by checking adjacent 2 bits in the result of the arithmetic operation. The above example of subtraction shows EE less than 15 greater than =xe2x80x9c1xe2x80x9d at which the canceling occurs. In order to convert the position of the canceling to a binary number, a priority encoder is used because the most significant bit of the value xe2x80x9c1xe2x80x9d in the EE less than i greater than  has a significant meaning. By passing the EE less than i greater than  through the priority encoder, the position at which the canceling occurs can be thereby represented by the binary number.
In these method described above, the canceling position is detected from the most significant bit of the result toward the least significant bit. However, the position of the canceling is changed by a carry signal propagated from a lower significant bit. In the above example, a carry signal is propagated from the bit number  less than 7 greater than . If the carry propagation does not occur, the position of the canceling is shifted rightward by one bit. That is, the canceling prediction by the above two methods includes one bit prediction error.
By the way, the normalization process performs a left shifting operation based on the result obtained by the canceling prediction circuit. However, because the result of the canceling prediction circuit includes an one bit prediction error, it must be necessary to perform the shift operation for the one bit error compensation immediately after the left shifting process for the normalization.
The one bit prediction error can be detected by checking the most significant bit in the arithmetic result that has been normalized. By using the detection result, it may be judged whether the compensation operation for one bit error is necessary or not.
The Japanese Laid open publication number JP-A-10/6026 proposed and disclosed a method to detect the one bit prediction error with the canceling prediction operation, simultaneously.
Next, a description will be given of the configuration of conventional floating point execution units.
FIG. 2 shows an example of a conventional typical floating point execution unit including a conventional canceling prediction circuit (a leading zero anticipator).
In the conventional floating point execution unit shown in FIG. 2, a comparison of exponent parts is executed before addition and subtraction, and then a mantissa part of the operand having the smaller exponent part based on the comparison result is shifted to the right direction (alignment). In addition to this operation, the normalization (left shifting) is performed after subtraction (or addition).
In the conventional floating point execution unit having the above configuration, the canceling prediction circuit performs the canceling prediction by using two operands after the alignment of the mantissa parts before addition and subtraction.
The comparison circuit 1 performs the comparison of the difference of exponent parts in the operands. The pair of selectors 2 and 3 inverts one of the mantissa parts Fa less than 23:0 greater than  and Fb less than 23:0 greater than  in the operands, or does not invert any one based on the difference of exponent. After this operation, the right shifter 4 performs the right shifting (alignment) for the mantissa part in the operand having the smaller exponent part is executed.
The addition and subtraction unit 16 performs an addition or a subtraction of the mantissa parts Fa less than 23:0 greater than  and Fb less than 23:0 greater than  in the operands that have been aligned, and outputs the result of the addition or the subtraction to the left shifter 8.
At the same time, the mantissa parts Fa less than 23:0 greater than  and Fb less than 23:0 greater than  after the alignment are transferred to the canceling prediction circuit 6 and size comparison circuit 7. Thus, the canceling prediction and the addition subtraction operation are executed in parallel.
The left shifter 8 performs the normalization by executing the left shifting to shift the arithmetic result of the addition subtraction unit 5 by using a shift amount control signal as the result of the canceling prediction by the canceling prediction circuit 6.
Because the shift amount control signal as the execution result of the canceling prediction circuit 6 includes one bit prediction error, the error compensation shifter 9 performs the one bit error compensation shifting (left shifting) based on the prediction error signal provided from the prediction error detection circuit 10 that has been obtained following the left shifting for the normalization.
The prediction error detection circuit 10 detects an one bit error based on the prediction information from the canceling prediction circuit 6 and the comparison information from the size comparison circuit 7.
FIG. 3 shows a configuration of a conventional floating point execution unit whose operation speed is higher than that of the conventional floating point execution unit shown in FIG. 2. As shown in FIG. 4, the conventional floating point execution unit shown in FIG. 3 switches operation paths based on whether or not the value of the difference of the exponent parts Expa and Expb in the operands is not less than 2.
In the subtraction when the difference of the exponent parts in the subtraction is not less than 2, or in the addition, the addition subtraction processing is executed through the following path: The right shifter 13; the selectors 14 and 15; and the addition subtraction unit 16. In this case, the alignment of the mantissa parts is executed before the operation of the addition subtraction unit 16. At this time, because at most one bit normalization processing is necessary for the mantissa parts, it is not necessary to incorporate any dedicated barrel shifter. As a result, it is possible to reduce the operation time for the normalization of the mantissa parts after the execution of the addition subtraction unit 16 (see FIGS. 4 and 5).
On the other hand, in the subtraction when the difference of the exponent parts is not more than 1, because the alignment of the mantissa parts before the subtraction executed by the subtraction unit 5 is within one bit, it is not necessary to use any dedicated barrel shifter. However, because it is necessary to execute the normalization for the maximum 24 bits in the normalization processing for the mantissa parts after the subtraction, the dedicated 24 bit barrel shifter (the left shifter 8 shown in FIG. 3) is required.
The subtraction is executed through the following path in the floating point execution unit: The selectors 2 and 3; the subtraction unit 5 inverter 11; selector 12; the left shifter 8; and the error compensation shifter 9.
As described above, by switching the paths by the selector 17, one of which is used based on the difference of the exponent parts, it is possible to reduce the operation time for the alignments before and after the arithmetic operation and the operation time for, the normalization as shown in FIG. 5. This causes to increase the operation speed of the conventional floating point execution unit.
By the way, in the conventional floating point execution unit shown in FIG. 3, the canceling prediction is executed by supplying the two operands, which have been selected and inverted by the pair of the selectors 2 and 3, to the canceling prediction circuit 6 based on the difference of the exponents parts of the two operands. Accordingly, the timing of the shift amount control signal by the canceling prediction circuit 6 must be delayed, because the operation of the selectors 2 and 3 is executed after operation of the comparison circuit 1 to output the difference of the exponent parts. This causes to increase the total operation time of the floating point execution unit.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional floating point execution unit, capable of performing the canceling prediction operation without waiting the completion of the comparison of exponent parts in operands to be used for the alignment of the operands, and thereby capable of executing the arithmetic operation at high speed.
In accordance with one aspect of the present invention, a floating point execution unit in which a subtraction circuit executes a subtraction operation only when a difference of exponent parts in two operands as floating point numbers is 1, 0, and xe2x88x921. This floating point execution unit comprises a first selection circuit, a subtraction circuit, a second selection circuit, a left shifter circuit, an error compensation circuit, a canceling prediction circuit, and a prediction error detection circuit.
The first selection circuit aligns a carry of said mantissa parts in said two operands by selecting one of cases where one of said mantissa parts in said two operands is shifted by one bit and no mantissa parts are shifted, by comparing exponent parts in said two operands. The subtraction circuit executes a subtraction of said mantissa parts in said two operands after said alignment. The second selection circuit selects one of said subtraction result and an inverted value that is obtained by inverting said subtraction result. The left shifter circuit executes normalization operation for said selected one output from said second selection circuit. The error compensation circuit compensates a canceling prediction error in said subtraction result after said normalization operation. The canceling prediction circuit generates a canceling bit prediction signal of said subtraction result based on said mantissa parts of said two operands before said alignment executed by said first selection circuit, and then determines a position of said, canceling bit. The prediction error detection circuit generates a compensation signal to compensate a prediction error indicated by said canceling bit prediction signal from said canceling prediction circuit. In the floating point execution unit of the present invention, said left shifter circuit executes said normalization operation for said subtraction result by shifting it leftward from said position of said canceling bit generated by said prediction error detection circuit, and said error compensation circuit compensates said canceling prediction error for said subtraction result that has been normalized based on said compensation signal output from said prediction error detection circuit.
Because the canceling prediction circuit directly inputs the two operands before the size comparison operation for the exponent parts in the two operands, namely, before alignment, and then performs the prediction to determine the position of the canceling bit and also to detect the canceling error, it is possible to determine the position of the canceling bit when or before the subtraction circuit outputs the subtraction result. Accordingly, by using the position of the canceling bit, the normalization operation can be executed immediately following the subtraction circuit outputs the subtraction result without any waiting and the following canceling error compensation operation can also be executed. Thereby, the floating point execution unit can perform at high speed.
In accordance with another aspect of the present invention, said canceling prediction circuit comprises:
a first canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 1;
a second canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is xe2x88x921;
a third canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 0 and said difference of said mantissa parts in said two operands is positive;
a fourth canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 0 and said difference of said mantissa parts in said two operands is negative;
a first selection circuit for selecting one of said canceling bit prediction signals generated by said first canceling bit prediction signal generation circuit and said third canceling bit prediction signal generation circuit when said difference of said exponent parts in said two operands is 1 or 0,
a second selection circuit for selecting one of said canceling bit prediction signals generated by said second canceling bit prediction signal generation circuit and said fourth canceling bit prediction signal generation circuit when said difference of said exponent parts in said two operands is xe2x88x921 or 0,
a first canceling bit position determination circuit for determining a position of said canceling bit based on said canceling bit prediction signal selected by said first selection circuit;:
a second canceling bit position determination circuit for determining a position of said canceling bit based on said canceling bit prediction signal selected by said second selection circuit; and
a third selection circuit for selecting one of said positions of said canceling bits determined by said first canceling bit position determination circuit and said second canceling bit position determination circuit based on a sign of said difference of said mantissa parts in said two operands.
In accordance with another aspect of the present invention, said canceling prediction circuit comprises:
a first canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 1;
a second canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is xe2x88x921;
a third canceling bit prediction signal generation circuit for generating said canceling bit prediction signal for said subtraction result when said difference of said exponent parts in said two operands is 0 without comparing said mantissa parts of said two operands;
a first selection circuit for selecting one of said canceling bit prediction signals generated by said first canceling bit prediction signal generation circuit, said second canceling bit prediction signal generation circuit, and said third canceling bit prediction signal generation circuit according to said values 1, xe2x88x921, and 0 of said difference of said exponent parts in ;said two operands; and
a canceling bit position determination circuit for determining a position of said canceling bit based on said canceling bit prediction signal selected by said first selection circuit.
In accordance with still another aspect of the present invention, a floating point execution unit for switching operation procedures according to absolute values (that are not less than 2 and less than 2) of a difference of exponent parts in two operands as floating point numbers.
This floating point execution unit comprises an addition subtraction unit, a subtraction unit, an exponent part comparison unit, a right shifter;
a size comparison unit, a canceling prediction circuit having a canceling bit prediction signal generation circuit and a canceling bit position determination circuit, a canceling error detection circuit, a left shifter; and an error compensation shifter.
The addition subtraction unit performs an addition and performs a subtraction when said absolute value of said difference of said exponent parts in said two operands is not less than 2. The subtraction unit performs only a subtraction when said absolute value of said difference of said exponent parts in said two operands is less than 2. The exponent part comparison unit calculates said difference of said exponent parts in said two operands. The right shifter performs an alignment of said mantissa parts in said two operands. The size comparison unit compares a size of said mantissa parts of said two operands. The canceling bit prediction signal generation circuit in the canceling prediction circuit predicts an amount of canceling occurred in a subtraction result of said subtraction unit within an error of one bit, and then generates a canceling bit prediction signal indicating a position of said canceling bit. Th e canceling bit position determination circuit in the canceling prediction circuit converts said canceling bit prediction signal to a binary number and outputs it as a canceling prediction signal. The canceling error detection circuit detects an error of said canceling prediction signal. The left shifter performs a normalization operation for said subtraction result from said subtraction unit by shifting said subtraction result leftward. The error compensation shifter compensates said error of said subtraction result based on said detection result detected by said prediction error detection circuit.
In said floating point execution unit of the present invention, said subtraction unit performs a subtraction operation between said mantissa parts of said two operands, or between one mantissa part and a shifted value obtained by shifting another mantissa part rightward in said two operands based on said difference of said exponent parts from said exponent comparison unit, and then outputs a subtraction result. Said canceling prediction circuit inputs directly said mantissa parts of said two operands and also inputs said difference of said exponent parts from said exponent comparison unit, and outputs said canceling prediction amount, caused by said subtraction operation by said subtraction unit, to said left shifter, Said prediction error detection circuit inputs directly said mantissa parts in said two operands, inputs said difference of said exponent parts from said exponent comparison unit, inputs said canceling prediction signal from said canceling prediction circuit, and inputs a comparison result of said mantissa parts output from said size comparison unit, and then outputs an error detection signal indicating a presence of said prediction error output from said canceling prediction circuit. Said left shifter performs said normalization operation by shifting leftward said subtraction result output from said subtraction unit based on a canceling prediction amount indicated by said canceling prediction signal output from said canceling prediction circuit. Said error compensation shifter compensates an error of said subtraction result normalized by said left shifter based on said error detection signal output from said prediction error detection circuit.
In the floating point execution unit in accordance with a further aspect of the present invention, said canceling prediction circuit predicts said canceling amount included in said subtraction result obtained by said subtraction unit within an error of; one bit. Said canceling bit prediction signal generation circuit generates said canceling bit prediction signal EE in the following cases (I), (IIa), (IIb), and (III) based on said difference of said exponent parts (Exaxe2x88x92Exb) in said two operands, where, said mantissa parts in said two operands xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are Fa less than n:0 greater than  and Fb less than n:0 greater than , each having xe2x80x9cn+1xe2x80x9d bit width, said exponent parts are Exa and Exb, a logical product is xe2x80x9candxe2x80x9d, a logical sum is xe2x80x9corxe2x80x9d, an exclusive logical sum is xe2x80x9cxorxe2x80x9d, and a logical not is xe2x80x9cnotxe2x80x9d:
(I) when Exaxe2x88x92Exb=1, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous two bits in said two operands is predicted by following logic:
EE less than i greater than =(not (P less than i greater than )) and (not (Z less than ixe2x88x921 greater than )),
wherein, when an integer i is i less than n,
G less than i greater than =(Fa less than i greater than ) and (not (Fb less than i+1 greater than )),
P less than i greater than =(Fa less than i greater than ) xor (not (Fb less than i+1 greater than )),
Z less than i greater than =(not (Fa less than i greater than )) and (Fb less than i+1 greater than ),
and
G less than n greater than =1, Z less than n greater than =P less than n greater than =0, Z less than xe2x88x921 greater than =Fb less than 0 greater than , G less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =not (Fb less than 0 greater than );
(IIa) Under the assumption of Exaxe2x88x92Exb=0 and Faxe2x88x92Fb greater than 0, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous two bits in said two operands is predicted by following logic:
xe2x80x83EE less than i greater than =(not (P less than i greater than )) and (not (Z less than ixe2x88x921 greater than )),
wherein, when an integer i is i less than n,
G less than i greater than =(Fa less than i greater than ) and (not (Fb less than i greater than )),
P less than i greater than =(Fa less than i greater than ) xor (not (Fb less than i greater than )),
Z less than i greater than =(not (Fa less than i greater than )) and (Fb less than i greater than ),
and
P less than n greater than =1, G less than n greater than =Z less than n greater than =0, Z less than xe2x88x921 greater than =0, G less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =1;
(IIb) under assumption of Exaxe2x88x92Exb=0 and Faxe2x88x92Fb less than 0, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous two bits in said two operands is predicted by following logic:
EE less than i greater than =(not (P less than i greater than )) and (not (G less than ixe2x88x921 greater than )),
wherein, when an integer i is i less than n,
G less than i greater than =(Fa less than i greater than ) and (not (Fb less than i greater than )),
P less than i greater than =(Fa less than i greater than ) xor (not (Fb less than i greater than )),
Z less than i greater than =(not (Fa less than i greater than )) and (Fb less than i greater than ),
and
P less than n greater than =1, G less than n greater than =Z less than n greater than =0, Z less than xe2x88x921 greater than =0, G less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =1;
(III) when Exaxe2x88x92Exb=xe2x88x921, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous two bits in said two operands is predicted by following logic:
EE less than i greater than =(not (P less than i greater than )) and (not (G less than ixe2x88x921 greater than )),
wherein, when an integer i is i less than n,
G less than i greater than =(not Fb less than i greater than ) and (Fa less than i+1 greater than )),
P less than i greater than =(not Fb less than i greater than ) xor (Fa less than i+1 greater than )),
Z less than i greater than =Fb less than i greater than  and (not (Fa less than i+1 greater than )),
and
Z less than n greater than =1, G less than n greater than =P less than n greater than =0, G less than xe2x88x921 greater than =Fa less than 0 greater than , Z less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =not(Fa less than 0 greater than ).
In the floating point execution unit, said canceling bit position determination circuit is two for two cases in which said difference of said mantissa parts is positive or assumed as positive, and said difference of said mantissa parts is negative or assumed as negative, and said canceling bit position determination circuit outputs said canceling bit position in binary number expression which is a most significant bit xe2x80x9cixe2x80x9d in said EE less than i greater than =xe2x80x9c1xe2x80x9d, and selects one of said canceling bit positions in said two cases based on said value (Faxe2x88x92Fb) output from said size comparison circuit. With said canceling bit position determination circuit, said canceling prediction error detection circuit determines the values G(xe2x88x921) less than kxe2x88x921 greater than  and Z(xe2x88x921) less than kxe2x88x921 greater than , where,
P(k) less than k greater than =P less than k greater than ,
G(k) less than k greater than =G less than k greater than ,
Z(k) less than k greater than =Z less than k greater than ,
P(k) less than k+1 greater than =(P(k+1) less than k+1 greater than ) and (P(k) less than k greater than ),
G(k) less than k+1 greater than =(G(k+1) less than k+1 greater than ) and {(P(k+1) less than k+1 greater than ) and (G(k) less than k greater than )},
Z(k) less than k+1 greater than =(Z(k+1) less than k+1 greater than ) or {(P(k+1) less than k+1 greater than ) and (Z(k) less than k greater than )},
and
P(m) less than k greater than =(P(n) less than k greater than ) and {(P(m) less than nxe2x88x921 greater than ) (m less than n less than k),
G(m) less than k greater than =G(n) less than k greater than  or {(P(n) less than k greater than ) and (G(m) less than nxe2x88x921 greater than )}(m less than n less than k),
Z(m) less than k greater than =Z(n) less than k greater than  or {(P(n) less than k greater than ) and (Z(m) less than nxe2x88x921 greater than )}(m less than n less than k), and
said canceling prediction error detection circuit selects said G(xe2x88x921) less than kxe2x88x921 greater than  when (Faxe2x88x92Fb) less than 0 that is output from said size comparison circuit, and said Z(xe2x88x921) less than kxe2x88x921 greater than  when (Faxe2x88x92Fb) greater than 0 that is output from said size comparison circuit.
In the floating point execution unit in accordance with another aspect of the present invention, said canceling prediction circuit predicts a canceling amount included in said subtraction result obtained by said subtraction unit within an error of one bit. Said canceling bit prediction signal generation circuit generates said canceling bit prediction signal EE in the following logic cases (I), (II), and (III) based on said difference: of said exponent parts (Exaxe2x88x92Exb) in said two operands, where, said mantissa parts in said two operands xe2x80x9caxe2x80x9d and xe2x80x9cbxe2x80x9d are Fa less than n:0 greater than  and Fb less than n:0 greater than , each having xe2x80x9cn+1xe2x80x9d bit width, said exponent parts are Exa and Exb, a logical product is xe2x80x9candxe2x80x9d and a logical sum is xe2x80x9corxe2x80x9d, an exclusive logical sum is xe2x80x9cxorxe2x80x9d, and a logical not xe2x80x9cnotxe2x80x9d:
(I) when Exaxe2x88x92Exb=1, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous two bits in said two operands is predicted by following logic:
EE less than i greater than =(not (P less than i greater than )) and (not (Z less than ixe2x88x921 greater than )),
wherein, when an integer i is i less than n,
G less than i greater than =(Fa less than i greater than ) and (not (Fb less than i+1 greater than )),
P less than i greater than =(Fa less than i greater than ) xor (not (Fb less than i+1 greater than )),
Z less than i greater than =(not (Fa less than i greater than )) and (Fb less than i+1 greater than ),
and
G less than n greater than =1, Z less than n greater than =P less than n greater than =0, Z less than xe2x88x921 greater than =Fb less than 0 greater than , G less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =not (Fb less than 0 greater than );
(II) when Exaxe2x88x92Exb=0, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous three bits in said two operands is predicted by following logic:
EE less than i greater than =[P less than i+1 greater than  and {(Z less than i greater than  and (not (G less than ixe2x88x921 greater than ))) or (G less than i greater than  and (not (Z less than ixe2x88x921 greater than )))}] or [not (P less than i+1 greater than ) and {(Z less than i greater than  and (not(Z less than ixe2x88x921 greater than ))) or (G less than i greater than  and (not (G less than ixe2x88x921)))}],
wherein, when an integer i is i less than n,
G less than i greater than =(Fa less than i greater than ) and (not (Fb less than i greater than )),
P less than i greater than =(Fa less than i greater than ) xor (not (Fb less than i greater than )),
Z less than i greater than =(not (Fa less than i greater than )) and (Fb less than i greater than ),
and
P less than n greater than =1, G less than n greater than =Z less than n greater than =0, Z less than xe2x88x921 greater than =0, G less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =1; and
(III) when Exaxe2x88x92Exb=xe2x88x921, said canceling bit prediction signal EE to indicate said predicted position of said canceling bit caused in subtraction result between continuous two bits in said two operands is predicted by following logic:
EE less than i greater than =(not (P less than i greater than )) and (not (G less than ixe2x88x921 greater than )),
wherein, when an integer i is i less than n,
G less than i greater than =(not Fb less than i greater than ) and (Fa less than i+1 greater than )),
P less than i greater than =(not Fb less than i greater than ) xor (Fa less than i+1 greater than )),
Z less than i greater than =Fa less than i greater than  and (not (Fa less than i+1 greater than )),
and
Z less than n greater than =1, G less than n greater than =P less than n greater than =0, G less than xe2x88x921 greater than =Fa less than 0 greater than , Z less than xe2x88x921 greater than =0, and P less than xe2x88x921 greater than =not(Fa less than 0 greater than ).
In the floating point execution unit, said canceling bit position determination circuit outputs said canceling bit position in binary number expression which is a most significant bit xe2x80x9cixe2x80x9d in said EE less than i greater than =xe2x80x9c1xe2x80x9d.
with said canceling bit position determination circuit, said canceling prediction error detection circuit determines the values G(xe2x88x921) less than kxe2x88x921 greater than  and Z(xe2x88x921) less than kxe2x88x921 greater than , where,
P(k) less than k greater than =P less than k greater than , G(k) less than k greater than =G less than k greater than , Z(k) less than k greater than =Z less than k greater than ,
P(k) less than k+1 greater than =(P(k+1) less than k+1 greater than ) and (P(k) less than k greater than ),
G(k) less than k+1 greater than =(G(k+1) less than k+1 greater than ) and {(P(k+1) less than k greater than ) and (G(k) less than k greater than )},
Z(k) less than k+1 greater than =(Z(k+1) less than k+1 greater than ) and {(P(k+1) less than k greater than ) and (Z(k) less than k greater than )},
and
P(m) less than k greater than =(P(n) less than k greater than ) and {(P(m) less than nxe2x88x921 greater than )(m less than n less than k),
G(m) less than k greater than =G(n) less than k greater than  or {(P(n) less than k greater than ) and (G(m) less than nxe2x88x921 greater than )}(m less than n less than k),
Z(m) less than k greater than =Z(n) less than k greater than  or {(P(n) less than k greater than ) and (Z(m) less than nxe2x88x921 greater than )}(m less than n less than k), and
said canceling prediction error detection circuit selects said G(xe2x88x921) less than kxe2x88x921 greater than  when (Faxe2x88x92Fb) less than 0 that is output from said size comparison circuit, and said Z(xe2x88x921) less than kxe2x88x921 greater than  when (Faxe2x88x92Fb) greater than 0 that is output from said size comparison circuit.